Semiconductors, which have been widely used for data processing for performing various processes according to instruction programs stored in a memory, controls execution of conditional branches in such a manner that when a conditional branch that branches to an address depending on whether or not the branch is taken is performed, an instruction fetch is performed for the predicted conditional branch and, if the branch is taken and the predicted and performed instruction fetch is right, the operation is continued, or if it is wrong, the operation is aborted and the instruction is re-executed.
One such prior-art semiconductor device will be described with reference to FIGS. 13 and 14.
FIG. 13 is a block diagram showing a configuration of a semiconductor device according to a prior art. As shown in FIG. 13, the prior-art semiconductor device consists of an instruction memory 1 storing as data an instruction program consisting of instruction codes, an instruction fetch block (hereinafter abbreviated to IFB) 2 for fetching instruction program data 6 from the instruction memory 1, a decode block (hereinafter abbreviated to DECB) 3 for decoding an instruction code 7 constituting the instruction program, and an execution block (hereinafter abbreviated to EXB) 4 for executing an instruction according to a control signal 8 associated with a decoded instruction.
In this configuration, an address 5 is inputted from the IFB 2 into the instruction memory 1, the data 6 is outputted from the instruction memory 1 to the IFB 2, the instruction code 7 is outputted from the IFB 2 to the DECB 3, the control signal 8 is outputted from the DECB 3 to the EXB 4, and a conditional-branch-taken signal (hereinafter abbreviated to BRTKN) 9 is inputted from the EXB 4 to the IFB 2 and the DECB 3. A system clock signal CLK is inputted into each block and pipeline processing is performed in accordance with the timing of the same CLK.
An operation for handling and executing a conditional branch instruction performed in the prior-art semiconductor device configured as describe above will be described below.
FIG. 14 is a timing diagram of executing a conditional branch instruction in the prior-art semiconductor device. In the period a in FIG. 14, a subtraction SUB D2, D1 is fetched in IFB 2.
In the period b, a conditional branch instruction BEQ disp8 is fetched in the IFB 2 and the SUB D2, D1 is decoded in the DECB 3. The conditional branch instruction BEQ disp8 causes a branch if a zero flag is set to 1 by the previous flag changing instruction. That is, the instruction causes the branch when the result of an operation is zero and otherwise causes the next instruction to be executed without causing a branch.
In the period c, the next, normal instruction AND D0, D1 is fetched in the IFB 2, the BEQ disp8 is decoded in the DECB 3, and the SUB D2, D1 is executed in the EXB 4. If the result of the operation is zero (the zero flag is set to 1), a conditional-branch-taken signal BRTKN 9 is generated in the period c (the HI level).
In the period d, the branch target instruction MOV D2, A0 is fetched in the IFB 2 in accordance with the BRTKN 9. Although the AND D0, D1, which has been fetched based on the prediction that the branch would not be taken, is decoded in the DECB 3, the BEQ disp8 is executed in the EXB 4. That is, the decoding of the MOV D2, A0 in the DECB 3 is cancelled in accordance with the BRTKN 9.
In the period e, the branch target instruction MOV D2, A0 is decoded in the DECB 3 and no operation is performed in the EXB 4 because the decoding of the AND D0, D1 has been canceled.
In the period f, the branch target instruction MOV D2, A0 is executed.
In such a prior-art semiconductor device described above has the problem that if a predicted instruction fetch is performed but the prediction is wrong, that is, if the conditional branch is taken, the execution of the instruction fetched is cancelled and therefore the execution cycle is wasted by the execution of the mispredicted instruction fetch, leading to performance degradation.